The reduction in memory cell area is required for high density DRAM ULSIs. This causes reduction in capacitor area, resulting in the reduction of the capacitance. A memory cell for each bit to be stored by the semiconductor DRAM typically consists of a storage capacitor and an access transistor. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits. The capacitor type that is most typically used in DRAM memory cells are planar capacitors, which are relatively simple to manufacture.
In order to achieve high performance (i.e. high density), memory cells in DRAM technology must be scaled down to the submicrometer range. Further, the size of the capacitor decreases, the capacitance of the capacitor also decreases. Similarly, the size of the charge capable of being stored by the capacitor decreases. This results in the capacitor being very susceptible to .alpha. particle interference. Additionally, as the capacitance decreases, the charge held by storage capacitor must be refreshed often. A simple stacked capacitor can not provide sufficient capacitance, even with high dielectric Ta.sub.2 O.sub.5 films as the capacitor insulator.
Prior art approaches to overcom these problems have resulted in the development of the trench capacitor (see for example U.S. Pat. No. 5,374,580) and the stacked capacitor. The trench capacitor has the well-known problem of "gated diode leakage," which is the leakage of current resulting in the trench capacitor failing to hold a charge. Reducing the thickness of the dielectric also can improve the capacitance of the capacitor, but this approach is limited because of yield and reliability problems.
A capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) polysilicon storage node has been developed (see "A Capacitor-Over-Bit-Line Cell With Hemispherical-Grain Storge Node For 64 Mb Drams", M. Sakao etc. microelectronics research laboratories, NEC Corporation). The HSG-Si is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous-Si to polycrystalline-Si. Further, a cylindrical capacitor using Hemispherical-Grained Si has been proposed (see "A New Cylindrical Capacitor Using Hemispherical Grained Si For 256 Mb DRAMs", H. Watanabe et al., Tech Dig, December 1992, pp.259-262).
Another way to form the hemispherical grained Si has been disclosed by M. Yoshimaru (IEEE IEDM-90, p.659) and H. Watanabe et al. (see "J. Appl. Phys. 71(7) p.3538, 1992). The hemispherical grained Si can be formed by using LPCVD at a temperature about 560-600.degree. C. Further, a crown shape capacitor or cylindrical structure have also been disclosed. However, the formation of the cylindrical structure capacitor and the crown shape capacitor are very complex. They also have reliable, stable problems that have to be overcome. In addition, a porous silicon can be formed by using an in-situ doped polysilicon in phosphoric acid solution at 150.degree. C. (H. Watanabe et al, Symposium on VLSI Technology p.17,1993).